Analog Dynamical-System Machines

Long-Term Research Objective: We aim to establish Rice as the world’s leading center for analog Dynamical-System Machine (DSM) computing. This is a new computing paradigm that replaces, not accelerates, digital logic. We envision a complete computing stack atop a programmable DSM built in standard CMOS, with no exotic materials, photonics, or cryogenics. DSM emulates target dynamic systems on a chip and lets continuous-time physical relaxation produce the solution. It plays three roles at once. It is a learned model of the target system, with parameters living in analog couplings. It is the hardware that executes the model by passively relaxing charges and voltages across physically coupled networks. And it is a real-time digital twin, or more accurately an “analog twin”, of the target dynamics, with no instruction stream and no iterative time stepping. This is fundamentally different from all the digital or analog accelerators developed for AI or other domain-specific workloads today, which all aim to accelerate existing algorithms designed for digital processors. Specifically, our DSM will use capacitors to represent multi-bit state nodes, and programmable coupling networks to define the energy function and the dynamics that govern how those states evolve. A novel pulse-width modulation (PWM) mixed-signal coupling primitive will enable scalable, practical, and reconfigurable modes covering matrix inversion, QUBO, HUBO, and multi-bit dynamic systems.

Why This Matters Now?

(1) The AI scaling wall is here. Frontier models reach hundreds of billions of parameters because polynomial-time matrix multiplication must emulate combinatorial reasoning. Native combinatorial and dynamical system primitives are the missing piece. (2) Mission-critical infrastructure cannot wait for the cloud. Power grids, scientific instruments, and 6G base stations all demand twins that are simultaneously fast (microsecond), efficient (milliwatt), and physically faithful. Numerical solvers are too slow; AI surrogates are too power-hungry and unreliable. No conventional approach satisfies all three. (3) DSM hardware and system research are booming. Recent DARPA and DOE programs, including some participated by Yang and Geng, have facilitated early research into unconventional computing based on analog dynamics, mostly targeting Ising and SAT solvers. The efforts have led to successful demonstrations of silicon prototypes and algorithmic and application explorations of such solvers. Expanding the concept beyond combinatorial optimization is a massive opportunity.

We aim at a new computational primitive that complements transformers and classical algorithms to open up a fresh design axis for AI, control, and optimization. We have identified four flagship application domains, each anchored in a Momentous Premier Research pillar. (1) Compact AI: Our 9M-parameter DSM-coupled model already exceeds 671B-class LLMs by 30+ points on Sudoku, Maze, and ARC-AGI dense reasoning, projecting orders-of-magnitude reductions in inference energy. (2) Future 6G Baseband: A single Hamiltonian collapses ML MIMO and LDPC decoding into one analog relaxation. Early evaluations on QuBRIM shows LDPC decoder at BER 4×10⁻⁸ and 1.29 pJ/bit/iter (2.4× to 7.6× SoTA 5G ASICs) project 10× to 100× lower baseband energy. (3) Thriving Urban Communities: Mapping the Swing Equation directly to circuit dynamics; our DS-TDDE/DS-TIDE prototypes deliver MAE one to three orders of magnitude better than PINN, UNet, and FNO at 10³× speedup, 10⁵× lower energy, and sub-microsecond latency. PNNL grid-data partnership is in place. (4) Scientific Discovery: Sub-microsecond latency at 20–348 mW power on representative PDE workloads, already published at MICRO and ISCA, with Geng currently serving as co-PI on two DOE AI-for-science efforts (FES ignition; OE grid stability). Finally, as a foundational computing platform, this cluster easily crosscuts with other clusters on vision, AI, theory, dgital twins, energy, and human-centered intelligent systems.

Why Rice, Why This Team? The combination of expertise required does not exist as one tightly integrated capability anywhere else. Among active researchers working on relevant topics, some focus on circuit design for well-known combinatorial optimization problems (e.g., Georgia Tech, Michigan, Minnesota) without exploring co-designs for new models and broader applications, while others focus on application and system explorations but lack hardware capability (e.g., Princeton, Stanford). We can integrate the full stack from algorithm to silicon to system and application. Yang (PI) has > 50 mixed-signal CMOS silicon chips for sensing and computing ting, with pioneering research in analog and analog / in-memory computing. Geng (Co-I) leads the DS-AI line of work, the most established research program in the community for turning dynamical-system substrates into AI primitives, published in Neurips, ICLR, ICML, ISCA, MICRO. He is co-PI on two active DOE AI-for-science projects in fusion ignition and grid stability. Mamouras (Co-I) leads programming language and compiler research for specialized hardware. Yang and Mamouras have collaborated closely for 4 years on hw/sw co-design, converting a $150K Rice Faculty Initiative Fund award into joint papers in top-tier conferences (ISCA, MICRO, HPCA, ASPLOS, PLDI) and two NSF medium-scale grants totaling $2 million. Yang and Geng labs have also started collaborating for over a year, meeting weekly, under a joint DARPA program on analog computing for CNN. Their recent joint paper was accepted as ICML Spotlight.