Some 13 percent of the workforce in high-performance computing, the vanguard of the nation’s computational power, is female.

“We should be appalled and ashamed by that. Studies show that 80 percent of women in computing say they love their jobs, but 56 percent of them leave their organization at a mid-level point in their careers. There’s a lot of work to be done,” said Toni Collis, chair and co-founder of Women in High Performance Computing.

Collis was addressing an unofficial but recurrent theme – diversity in computing -- at the 12th-annual Oil & Gas High-Performance Computing Conference at Rice University. Hosted March 4-6 by the Ken Kennedy Institute for Information Technology, the event drew a record turnout, 590 leaders from the oil and gas industry, the high-performance computing and information technology industries, and academics.

“Diversity means many things in these industries. If you ignore it, it won’t happen,” said Jan E. Odegard, executive director of Kennedy Institute and associate vice president in Rice’s office of information technology.

“In the overall computing workforce,” Collis said, “women hold 25 percent of the jobs. Rather than focus on having ‘diversity’ strategies, we need to focus on having more ‘inclusion’ strategies. We need to talk about policies that are beneficial for everyone.”

Lori Diachin, deputy director of the Exascale Computing Project (ECP), administered by the U.S. Department of Energy (DOE), said, “We don’t just want advancements in theoretical peak performance. 1018 FLOP/s is not enough. Massive amounts of theoretical computing does us no good if real applications can’t make use of it.”

Diachin stressed the importance of creating new algorithms (“adopting Monte Carlo vs. deterministic approaches”), application development, ease of use and diverse architectures. “Our goal,” she said, “is to develop and enhance the predictive capability of applications that are critical to DOE across science, energy and national security mission space.”

She said ECP has identified 25 applications that target problems in the United States, including national, energy and economic security, scientific discovery, the Earth system and health care. More than 80 software products are being developed for use on the next-generation architectures.

Forrest Norrod, senior vice president and general manager at AMD (Advanced Micro Devices), touted the efficacy of his company’s “chiplets.” Instead of manufacturing processors from silicon as single chips, the company’s new approach assembles them from multiple smaller pieces of silicon.

“You get more silicon per socket. It permits rapid architectural innovation, optimized to improve latency and power,” Norrod said.

The National Science Foundation awarded $60 million to the Texas Advanced Computing Center (TACC) to build nation’s fastest academic supercomputer. Called “Frontera,” the computer is expected to become operational later this year.

Since 2006, TACC has built and operated three supercomputers that debuted in the Top 10 most powerful systems in the world: Ranger (2008), Stampede1 (2012) and Stampede2 (2017). Another three systems debuted in the Top 25.

“Frontera’s architecture is in many ways ‘boring’ if you are an HPC journalist, architect or general supercomputer junkie. We have found that the way users refer to this kind of configuration is ‘useful,’” Satanzione said.

Frontera will operate for five years. The NSF funding will also support efforts to test an even more powerful supercomputer, 10 times as fast as Frontera, which may be deployed as the second phase of the project.

Last year, Intel celebrated its 50th anniversary. Trish Damkroger, vice president and general manager of Intel’s Data Center Group, reviewed the company’s history, including its development, in 1971, of the world’s first commercial microprocessor chip.

Intel’s latest innovation is a 3D packaging technology called Foveros, which stacks die in three-dimensional heterogeneous structures that combine logic and memory. It differs from the passive interposer and stacked memory technologies already available by broadening the 3D packaging concept to include high-performance logic such as CPU, graphics, and AI processors.

“No single transistor node is optimal across all design points,” Damkroger said. “While computing has grown at an exponential rate, memory performance only grew at a linear rate. Our solution is a converged memory/storage hierarchy.”

The first Foveros product will combine a high-performance 10-nanometer compute-stacked chiplet with a low-power 22FFL (Fin field effect transistor, low power) base die. “Intel’s strategy,” Damkroger said, “is to offer a mix of architectures deployed in various CPU, GPU, FPGA and accelerator sockets, all with scalable interconnect and a single software abstraction.”

Satoshi Matsuoka, director of the RIKEN Center for Computational Science, the largest supercomputing center in Japan, spoke on “Post-K: A Game-Changing Supercomputer for Convergence of HPC and Big Data/AI.”

“I am here to speak about the Post-K computer, how we design it, how we deploy it, and how it is not only designed to be good for HPC workloads but also for big data and AI. I joined the Riken Center in April 2018. Post-K was already underway and I was able to leverage years of experience from Tokyo Tech, my previous institution. With the TSUBAME series of computers, deployed in 2017, we had more than 10 million cores and it is still operational. There we pioneered the use of GPUs in the realm of HPC. Today, Riken operates the flagship K-computer, which was ranked as the fastest in the world in 2011.”

The Post-K computer will be housed in 400 racks with 150,000 nodes (about 8 million high-performance Arm v8.2 cores), and will at peak require about 40 MW of power for the facility.

Among the other speakers were Brent Gorda, senior director of HPC business for Arm, who spoke on “Arm in HPC,” and Detlef Hohl, chief scientist for computation and data science at Shell, who spoke on “High-Performance Computing and High-Performance Data Analytics, and What O&G Will Do about It in the Next 10 Years.”

This year’s conference included two keynotes and five plenary talks, an early career panel, four parallel sessions with a total of 20 talks selected from submitted abstracts. The conference concluded with a large student poster session. Four pre- and post-conference workshops were also held. For additional details on the conference organizers, sponsors and to review presentations and please visit the conferenced web page at http://rice2019oghpc.rice.edu/

Author: PATRICK KURP